The present invention is directed, in general, to semiconductor devices and, more specifically, to a method of etching a dielectric having a high dielectric constant.
As is well known, various semiconductor devices and structures are fabricated on semiconductor wafers in order to form operative integrated circuits (IC""s). These various semiconductor devices and structures allow fast, reliable, and inexpensive IC""s to be manufactured for today""s competitive computer and telecommunication markets. To keep such IC""s inexpensive, the semiconductor manufacturing industry continually strives to economize each step of the IC fabrication process to the greatest extent, while maintaining the highest degree of quality and functionality possible.
The use of different methods for manufacturing semiconductor devices has reached phenomenal proportions over the last decade. Equally phenomenal has been achievement of the ever-decreasing size of the semiconductor devices themselves. Such decreasing device dimensions inherently require that the thickness of dielectrics such as gate oxides, with in metal-oxide semiconductor field effect transistors (MOSFET), shrink as well. It is particularly desirable to reduce the thickness of the gate oxide in these devices, since the drive current in semiconductor devices increases as the thickness of the gate oxide decreases. Unfortunately, along with the trend toward thinner gate oxides comes the increased risk of reduced quality of the dielectric gate oxide layers. Even where ultra-thin high quality conventional dielectrics may be produced, high leakage currents and poor reliability limit their thickness to a value too large for the high-speed switching required today.
In response to these concerns, the use of dielectric films having a high dielectric constant (K) has gained popularity. Such high-K dielectric materials and processes for their incorporation into semiconductor devices and IC""s are being developed to eventually replace conventional gate oxides. In addition to a high-K value, new gate oxide candidates must satisfy other criteria if they are to be integrated into standard manufacturing processes. These include thermodynamic stability on silicon, low leakage current, and conformal growth. Many high-K dielectrics (10 less than K less than 80) have been proposed, such as TiO2, Ta2O5, SrTiO3, Al2O3, HfO2 and ZrO2; however, all fail some of the criteria listed above.
Another particular problem that inhibits the use of current high dielectric constant gate materials is the lack of a suitable dry etching process available to remove the gate dielectric layer after the gates have been formed. This process must remove the dielectric layer with a selectivity that is suitable with respect to the underlying substrate. Etchant selectivity refers to the relative rate at which the etchant removes various materials that may make up a semiconductor device. Thus, in a process of forming a gate by a current etching process, the gate dielectric layer may not be suitably etched before the underlying silicon is etched.
Accordingly, what is needed in the art is a method of forming a semiconductor device having a high dielectric constant oxide that may be satisfactorily etched and a method of manufacture therefor that does not suffer from the deficiencies of the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method comprises depositing a metal oxide containing a dopant and having a high dielectric constant on a substrate; wherein the metal is aluminum or silicon and the dopant is zirconium or hafnium and etching the doped metal oxide with a plasma containing a halogenated compound.
In another aspect, the present invention provides a method of manufacturing an integrated circuit. In this particular embodiment, the method includes metal depositing a metal oxide containing a dopant and having a high dielectric constant on a substrate; wherein the metal is aluminum or silicon and the dopant is zirconium or hafnium, etching the doped metal oxide with a plasma containing a halogenated compound and forming interconnects that interconnect the active devices to form an operative integrated circuit.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.